1. Field of the Invention
The present invention relates to a semiconductor memory device such as a dynamic random access memory (DRAM) and more particularly relates to a semiconductor memory device wherein, when redundant memory is provided, access time can be shortened and furthermore redundancy efficiency can be raised even when capacity is large.
2. Description of the Related Art
The capacity of semiconductor memory devices such as DRAMs is continually being increased. It has recently been reported that capacity has reached 1 Gigabit. In such large-capacity memories, redundant memory is provided in order to raise yield by rescuing defective bits, defective word lines, and defective bit lines. In particular, rescue of fixed defects produced by short-circuiting or disconnection of word lines or bit lines due to process factors is adopted in practically all memories. And in recent years techniques have even been proposed to substitute with cells of redundant memory defective bits whose refresh period has become short.
A memory including such a redundant memory has a circuit for deciding on redundancy wherein addresses to be substituted are stored in a PROM or the like, to decide whether these coincide with an input address or not. Typically such a circuit for deciding on redundancy is a circuit in which PROM elements such as fuses are incorporated at various different places in the circuit.
FIG. 9 is a layout diagram of a prior art memory provided with redundant memory. In this example, a redundant memory cell array 12 is provided in addition to memory cell array 10. In this case, as an example, only the redundant structure on the row side is shown. A word line WL in memory cell array 10 is selected and driven by a row decoder driver 14 that is supplied with a row address 30. The memory data of a memory cell provided at the point of intersection of word line WL and bit lines BL1, BL2 is then read onto bit lines BL1, BL2, sensed and amplified by sense amplifier 20 and applied to input/output circuit 22 through data buses Bus1, Bus2 and output from input/output terminal DQ. The output of sense amplifier 20 is selected by means of column decoder driver 18, which is supplied with a column address 32.
A defective word line is substituted with a redundant word line RWL in the redundant memory cell array. A row address corresponding to a defective word line is recorded in PROM in a circuit for deciding on redundancy 24. Circuit for deciding on redundancy 24 determines whether or not a supplied row address coincides with a recorded address.
FIG. 10 is a view showing an example of this circuit for deciding on redundancy. This circuit basically has an NOR circuit structure and comprises fuses f0, /f0, f1, /f1 constituting PROM cells that store a substitute address and N type transistors Q.sub.12, Q.sub.13, Q.sub.14 and Q.sub.15 to the gates of which an address is applied from outside, connected in series. P type transistor P.sub.10 and N type transistor Q.sub.11 are the circuits that activate the circuit for deciding on redundancy 24 by H level of redundancy decision timing signal 34.
Let us now provisionally assume that fuses f0 and f1 are melted if the substitution address is (A0, A1). Thereupon the operation of this circuit is as follows: redundancy decision timing signal 34 is normally L level and transistor Q.sub.11 is non-conductive, its output 36 being H level. When an address signal is then applied from outside, causing redundancy decision timing signal 34 to become H level, H level of output 36 is maintained only if the external address is (A0, A1)=(1, 1); if an address other than this is applied, a current path as shown by the broken line in the drawing is generated, causing output 36 to become L level. Signal 26 that selects memory cell array 10 is therefore L level in selection, and the signal 28 that selects redundant memory cell array 12 also goes into L level in selection.
As described above, in circuit for deciding on redundancy 24, PROM elements such as fuses which have large resistance or capacitance are present on the critical path of address determination, so the time required to determine the level of output 36 is long. Since, as shown in FIG. 9, a word decoder driver is selected by a decision signal 26, 28 after decision whether the address 30 from outside is the same as a substitution address or not, the speed of circuit for deciding on redundancy 24 is low, making the memory access time long.
Furthermore, if the number of addresses that must be compared by the circuit for deciding on redundancy 24 is large, the scale of the circuit for deciding on redundancy 24 needed for redundant memory becomes large. On the other hand, it is common structure in a large-capacity memory that the memory is divided for example into a plurality of banks, and each bank is further divided into a plurality of blocks. In this way, if the memory cell array is divided into a plurality and a redundant memory cell array is provided for each block, the number of addresses of the circuit for deciding on redundancy can be made small, enabling its scale to be reduced and so raising its speed of operation.
However, the redundant memory cell array provided for each block can only be used to substitute defective cells within the corresponding block. However, defective bit and/or defective word lines are not always generated in dispersed manner but may occur concentrated in a few blocks. And in fact defective bit and/or defective word lines can even occur in the redundant memory cell array itself.
Under these circumstances, with a memory cell array that is implemented in the form of small blocks, if redundant memory cell arrays are provided for each of these, the probability of rescue of defective bits or defective words is lowered. As mentioned above, if defects are present in the redundant memory cell array, the probability of rescue is to that extent lowered. Also, if defects are concentrated in a specific block, the capacity of the redundant memory at the specific block may be insufficient, making rescue impossible.